System-on-a-chip with multi-layered metallized through-hole interconnection

ABSTRACT

The present invention is directed to a high-performance system on a chip which uses multi-layer wiring/insulation through-hole interconnections to provide short wiring and controlled low-impedance wiring including ground planes and power supply distribution planes between chips.

BACKGROUND OF THE INVENTION

[0001] I. FIELD OF THE INVENTION

[0002] The present invention relates generally to integrated circuittechnology. More specifically, the invention relates to a multi-chipsystem which includes a chip carrier having a multi-layered metallizedthrough-hole interconnection and a method of making the same.

[0003] II. DESCRIPTION OF THE RELATED ART

[0004] There is a growing desire for a “system on a chip” as integratedcircuit technology enters the ultra large scale integration (ULSI ) era.Ideally, the industry would like to build a computing system byfabricating all the necessary integrated circuits on one substrate, ascompared with today's method of fabricating many chips of differentfunctions on multiple substrates. The concept of “system on a chip” hasbeen around since the very large scale integration (VLSI) era (early1980s), but even today, it is very difficult to implement such a trulyhigh-performance system on a single chip because of vastly differentfabrication processes and different manufacturing yields for variouslogic and memory circuits. With many diverse circuits, especially with amixture of analog and digital circuits, a low-impedance ground is alsorequired to suppress digital noise. High-speed synchronous digitalintegrated circuits require large switching currents which can inducenoise on the power distribution networks and ground busses due to finiteresistance and inductance in these circuits. Additionally, power supplynoise can have a tremendous effect due to simultaneous switching noisein CMOS integrated circuits. These problems are more severe inmixed-mode analog/digital circuits and require careful design of thepower distribution systems. Thus, based on current circuitimplementation, there is a need for a built-in ground plane adequate tohandle and dissipate noise which is also difficult to fabricate on asingle chip with other components. A buried ground plane is highlydesirable to provide a flat surface to which various chips, activecircuits, and passive components can be subsequently mounted.

[0005] To overcome some of these problems, a “system module” hasrecently been suggested in T. Mimura, et al, “System module: a newChip-on-Chip module technology,” Proc. of IEEE 1997 Custom IntegratedCircuit Conf., pages 437-442, 1997. This system module consists of twochips with a first chip stacked on a second chip in a structure calledChip-on-Chip (COC) using a micro bump bonding technology (MBB). Withthis technology, each chip can be fabricated to perform specifiedfunctions with optimum processing conditions. Then the individual chipscan be combined in a single packaged structure.

[0006] Recently, in U.S. patent application Ser. No. 09/144,307, by Ahnet al., a compact system module with built-in thermoelectric cooling isdescribed in which a memory chip is directly mounted on a microprocessorchip. In U.S. patent application Ser. No. 09/144,290, by the sameinventors of the '307 application, a scheme of high-performancepackaging in which individual chips are mounted on a silicon interposeris described. In another U.S. patent application Ser. No. 09/143,729, abuilt-it cooling channel was introduced for efficient removal of heatgenerated by many chips mounted on a silicon interposer. Furthermore, asilicon interposer with built-in active devices was also recentlydisclosed in U.S. patent application Ser. No. 09/144,197. Still further,an attempt to assemble a compact system using multi-chip moduletechnology for space-borne applications is disclosed by R. J. Jensen etal., in “Mission: MCM, Designing for Reliability in Harsh Environments,”Advanced Packaging, January, 1998, p. 22-26, in which decouplingcapacitors are an integral part of the system. Davidson et al. in anarticle entitled “Long Lossy Lines and Their Impact Upon Large chipPerformance,” IEEE Trans. On Component Packaging and Manufacturing, Pt.B., vol. 20., no. 4, p. 361-375, 1997, addresses key concerns inassembling many chips to a system module, namely, the length andresistance of the interconnect lines. Davidson, cites an example of asingle microprocessor chip partitioned into four smaller ASIC chips forhigher production yield and consequently lower cost, and suggestsmounting them on a single multichip module, called a die pack, such asillustrated here in FIGS. 1(a) and 1(b). With such a scheme, a long dataline can be reduced to a few millimeters. Also, see U.S. patentapplications Ser. No. 09/009,791, Ser. No. 09/199,442, Ser. No.09/247,680, Ser. No. 09/258,739 and Ser. No. 09/255,077 for relateddiscussions on mounting individual chips on a common carrier substrate.

[0007] While many improvements have been made in the multi-chip on asubstrate technology, there still remains a need for a high performancecompact system which provides controlled low-impedance wiring, includingthe ground and distribution plane wiring, between chips mounted on thesame and opposite side of a common substrate.

SUMMARY OF THE INVENTION

[0008] The present invention is directed to an apparatus and method ofmaking an apparatus for a high-performance system module which usesmulti-layer metallized through-hole interconnections on a chip carriersubstrate to provide short wiring and controlled low-impedance wiringbetween chips mounted on the carrier, the wiring including at least oneof a ground plane and a power distribution plane.

[0009] The term “substrate” used in the following description mayinclude any semiconductor-based structure that has an exposed siliconsurface. Structure must be understood to include silicon-on insulator(SOI), silicon-on sapphire (SOS), doped and undoped semiconductors,epitaxial layers of silicon supported by a base semiconductorfoundation, and other semiconductor structures. The semiconductor neednot be silicon-based. The semiconductor could be silicon-germanium,germanium, or gallium arsenide. When reference is made to substrate inthe following description, previous process steps may have been utilizedto form regions or junctions in or on the base semiconductor orfoundation.

[0010] The inventive method of the present invention comprises providinga chip carrier substrate, typically formed of silicon, with amulti-layer metallized through-hole interconnection. The through-holeinterconnection may be formed by: depositing a first insulating layer ofsilicon dioxide over a substrate; depositing a first ground plane orpower supply plane layer over the silicon dioxide layer; depositing asecond insulating layer over the first layer; depositing a signal linewiring layer over the second insulating layer; depositing a thirdinsulating layer over the signal line wiring layer; depositing another(second) ground plane or power supply plane layer over the thirdinsulating layer; and depositing a fourth insulating layer over thesecond ground plane or power supply layer. The carrier substrate can beused to carry and interconnect one or more chips as part of anintegrated package unit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The foregoing and other advantages and features of the inventionwill become more apparent from the detailed description of preferredembodiments of the invention given below with reference to theaccompanying drawings in which:

[0012] FIGS. 1(a)-1(b) illustrate an example of a prior art singlemicroprocessor chip partitioned into four smaller ASIC chips mounted ona multi-chip module, called a die pack;

[0013]FIG. 2 illustrates a cross sectional view of a substrate having athrough-hole interconnection in accordance with an exemplary embodimentof the present invention;

[0014]FIG. 3 is schematic drawing of a through-hole interconnection, topview in accordance with an exemplary embodiment of the presentinvention;

[0015]FIG. 4 is a schematic drawing of a through-hole interconnectioncross sectional view along line 4-4 shown in FIG. 3;

[0016]FIG. 5(a) illustrates a cross-sectional view of a controlledimpedance interconnect system and fabrication sequence in accordancewith an exemplary embodiment of the present invention;

[0017]FIG. 5(b) illustrates a cross-sectional view of a controlledimpedance interconnect system featuring interconnect wiring inaccordance with an exemplary embodiment of the present invention;

[0018]FIG. 6 illustrates the process for forming interconnect wiringbetween the signal line wiring layer and substrate;

[0019]FIG. 7 illustrates the process for forming interconnect wiringbetween the passive components and the signal line wiring layer; and

[0020]FIG. 8 illustrates a processor based system employing through-holeinterconnections in accordance with an exemplary embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE DRAWINGS

[0021] Referring now to the drawings, where like reference numeralsdesignate like elements, there is shown in FIG. 2 a chip carrier systemin accordance with an exemplary embodiment of the present invention. Itincludes a chip carrier formed as a substrate 17, e.g., a siliconsubstrate, on which passive or active circuit components 19, such asresistors, capacitors, inductors, transistors, etc., can be formed,which is covered by a multi-layer wiring/insulation layer 15 (describedin greater detail below), and on which a plurality of circuit chips aremounted. As illustrated in FIG. 2, the circuit chips may include one ormore of a microprocessor chip 23, DRAM chip 25, SRAM chip 27, ROM chip24, ASIC chip 28, or other chips which are mounted to the multi-layerwiring/insulation layer 15 through a Ball Grid Array 13. The chipcarrier is also provided with one or more through-holes 29 through whichthe multi-layer wiring/insulation layer 15 passes to make electricalconnection between chips mounted on opposite sides of the substrate 17.For simplicity, only one through-hole 29 is shown, but it should beunderstood that any number may be provided. Details of through-holefabrication for a silicon substrate were given recently in C.Christensen, et al., “Wafer through-Hole Interconnections with HighVertical Wiring Densities,” IEEE Trans. On Components, Packing andManufacturing Technology, Pt. A, vol. 19, no. 4, p. 516-522, 1996.Accordingly, a detailed description of how to form a through hole insubstrate 17 will not be repeated herein.

[0022]FIG. 3 is a top view of a through-hole 29 of FIG. 2 with upperlayers removed to show the signal line wiring layer 31, which passthrough the through-hole 29 and associated bond pads 33 which areconnected to the signal line wiring layer 31 through interconnect wiring60 (FIG. 4). A similar signal line wiring layer 31 and associated bondpads 33 are provided on the opposite side of the substrate 17. Thethrough-hole may be a hollowed rectangle, circle, or any other geometricshape. The chips, supported by substrate 17, are interconnected toinput/output, ground and power terminals by virtue of their mounting onbond pads 33. The through-hole 29 on the top surface illustrated in FIG.3 has sloping sidewalls 40, as also illustrated in FIG. 2. Forsimplicity, only 12 bond pads 33 are shown, but it should be appreciatedthat the number of bond pads 33 and associated leads from the signalline wiring layer 31 passing through the through-hole 29 may be largeror smaller. Typically the through-hole 29 size is 1 mm square at itssmallest opening dimension 22 (FIG. 2).

[0023]FIG. 4 is a cross sectional view along line 4-4 of FIG. 3illustrating the detailed multi-layer wiring/insulation layer 15. Themulti-layer 15 is formed on the substrate 17, which may also have activeand/or passive components 19 formed thereon. The multi-layer structureincludes a first insulating layer 35, e.g., a silicon dioxide layer,formed as a continuous layer over both sides of substrate 17 and in thethrough-hole 29, a first conductive ground plane layer 37 a oralternatively a conductive power supply distribution plane layer 37 bformed as a continuous layer over the first insulating layer 35, asecond insulating layer 39 formed as a continuous layer over the layer37 a or 37 b, a signal line wiring layer 31 formed as a wiring patternover the second insulating layer 39, a third insulating layer 41 formedas a continuous layer over the signal line wiring layer 31, anotherground plane layer 43 a or alternatively another conductive power supplydistribution plane layer 43 b formed as a continuous layer over thethird insulating layer 41, and a fourth insulating layer 45 formed as acontinuous layer over layer 43 a or 43 b.

[0024] The signal line wiring layer 31 is electrically connected tointerconnect wiring 60, 62. As noted, the interconnect wiring 60electrically connects the signal lines of wiring layer 31 with bond pads33. The interconnect wiring 62 electrically connects the active and/orpassive structures formed on substrate 17 to the signal wiring layer 31.The bond pads 33 provide locations on which one or more of the chips 23,24, 25, 27 are mounted by for example, the Ball Grid Array technique,thereby electrically connecting the active and/or passive componentsfabricated on the substrate 17 to one or more of the chips 23, 24, 25,27 through wiring layer 31.

[0025] The chip carrier system illustrated in FIGS. 2-4 contains shortcontrolled impedance wiring paths between the chips mounted on bothsides of substrate 17 through the multi-layer wiring/insulation layer 15which passes through the through-hole 29.

[0026]FIG. 5(a) is a cross sectional view of a controlled impedanceinterconnect system of FIG. 4 showing the fabrication sequence. Inpractice, the first ground plane 37 a or the power supply distributionplane 37 b is first fabricated by depositing a highly conductive layer,such as copper or aluminum, by simple evaporation, sputtering orelectroplating with a typical thickness of about 3 to 5 μm over a firstinsulating layer 35, e.g. silicon dioxide, previously deposited over thesubstrate 17 by, for example, CVD, typically to a thickness of about 0.1to 0.5 μm. A second insulating layer 39 is deposited over this highlyconductive layer 37 a or 37 b in step 2. This second insulating layer 39preferably is silicon dioxide deposited by chemical vapor deposition(CVD) to a thickness of about 0.5 to 4 μm. Alternatively, an insulatorwith a lower dielectric constant, such as polyimide with ∈=3, may bedeposited by spin coating followed by curing, if required by theelectrical design. The next step is to fabricate the patterned signallines 31, which are typically about 6 to 10 μm wide, by employingoptical lithography of a photoresist followed by additive metallization,such as liftoff by evaporation or electroplating, both of which arelow-temperature processing techniques. In step 4 a third insulatinglayer 41 is deposited over the signal lines 31. Once again, the thirdinsulating layer 41 is preferably a layer of silicon dioxide depositedby CVD to a thickness of at least 50% greater than the signal linewiring layer 31 conductor thickness to ensure good step coverage at thesignal line 31 conductor corners. If a lower dielectric constant isdesired, a lower dielectric constant polymer, such as polyimide, can bedeposited by spin coating. In step 5 a planar conductor, as anotherground plane 43 a or alternatively another conductive power supplydistribution plane 43 b, is deposited over the third insulating layer 41to a thickness of 3 to 5 μm as was done in step 1. It may also bedesirable to planarize the third insulating layer 41 to provide a flatsurface so that when planar conductor 43 a or 43 b is formed it issubstantially planar. The final step is to deposit a fourth insulatinglayer 45 over the planar conductor 43 a or 43 b.

[0027]FIG. 5(b) illustrates a cross sectional view of the controlledimpedance interconnect system of FIG. 5(a) with the interconnect wiring60,62 and bond pads 33. FIGS. 6 and 7 illustrate the steps needed toprovide interconnect wiring 60, 62 (FIG. 5(b)) between: (i) the activeand/or passive components 19 formed on substrate 17 and the signal linewiring layer 31 and (ii) the signal line wiring layer 31 and the circuitchips 23, 24, 25, 27.

[0028] In order to get a signal from the active and/or passivecomponents 19 to the signal lines 31, interconnect wiring 62, a signalconductor, must be fabricated. Materials and techniques for forming suchinterconnect wiring 62 are commonly known in the art. However, FIG. 6provides a flow chart illustration of one exemplary technique inaccordance with this invention. After step 2 of FIG. 5(a) is completed,one or more holes are etched through the second insulating layer 39,layers 37 a/37 b and 35 to the active and/or passive components 19.Based upon the size of interconnect wiring (conductor) 62 needed thehole may be formed by wet etching or dry etching, such as reactive ionor plasma etching, see step 502. Next, in step 504, an hole insulator 72is deposited using CVD. This is to shield the soon to be depositedinterconnect wiring 62 from the layers which are between the signal linewiring layer 31 and the substrate 17. The hole insulator 72 can be SiO₂,Si₃N₄ or other commonly known oxides. Lastly, the interconnect wiring 62is deposited in step 506. The interconnect wiring can be aluminum orcopper, for example. The interconnect wiring 62 is deposited in theinsulated hole by any commonly known process, e.g. evaporation,electroplating, etc. Step 506 can occur at the same time as depositionof the signal wiring layer 31 (step 3 of FIG. 5(a)) in order to increaseefficiency and attain maximum conductivity. The interconnect wiring 62is then used to carry a signal from the active and/or passive components19 to the signal wiring layer 31.

[0029]FIG. 7 illustrates a similar process as that described in FIG. 6with the exception that FIG. 7 relates to depositing interconnect wiring60 from the bond pads 33 of circuit chips 23, 24, 25, 27, 28 to thesignal line wiring layer 31. For interconnect wiring 60 one or moreholes are etched in step 602 and a hole insulator is deposited in step604 as in the fabrication of interconnect wiring 62. However, thisprocess is performed after the deposition of the fourth insulating layer45 (step 6, FIG. 5(a)). The last step, again, is to deposit theinterconnect wiring 62 in step 606. When interconnect wiring 62 isdeposited, the bonds pads 33 may all be fabricated in a one stepmetallization to increase efficiency and conductivity.

[0030] The substrate 17 with multi-layer wiring/insulation layer 15 andassociated circuit chips 23, 24, 25 , 27, 28 may all be encapsulated ina single integrated package unit composed of a plastic composite. Insuch an implementation multiple exterior pins are needed to interfacethe integrated package unit to a circuit board for communication withother components of a system.

[0031]FIG. 8 illustrates a processor-based system 102, including centralprocessing unit (CPU) 112, memory devices 108, 110, input/output (I/O)devices 104, 106, floppy disk drive 114 and CD ROM drive 116. All of theabove components communicate with each other over bus 118. The centralprocessing unit (CPU) 112, and one or more of the memory devices 108,110 are fabricated as one or more chips which can be mounted onto a chipcarrier 17, as illustrated in FIG. 2, with through-hole interconnectionsin accordance with the present invention as described above.

[0032] As noted, the present invention provides for an apparatus andmethod of making the same which results in a chip carrier system withshort through-hole interconnections and with a low impedance.

[0033] It is to be understood that the above description is intended tobe illustrative and not restrictive. Many variations to theabove-described method and structure will be readily apparent to thosehaving ordinary skill in the art. For example, the conducting andinsulting layers can be constructed of many different commonly knownmaterials. In addition, alternative insulating and conducting layers canbe formed within the multi-layer wiring/insulating layer 15 and anynumber of conductive and insulating layers can be used.

[0034] Accordingly, the present invention is not to be considered aslimited by the specifics of the particular structures which have beendescribed and illustrated, but is only limited by the scope of theappended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A chip mounting system comprising: a substratefor mounting at least one chip, said substrate having at least onethrough-hole; and a multi-layer structure covering both sides of saidsubstrate and passing through said at least one through-hole, saidmulti-layer structure comprising at least one conductive plane and asignal wiring layer, said at least one conductive plane and said signalwiring layer having an insulating layer interposed between them.
 2. Thechip mounting system of claim 1, wherein said conductive plane comprisesa first ground plane.
 3. The chip mounting system of claim 2, whereinsaid first ground plane is at least 3 μm thick.
 4. The chip mountingsystem of claim 2, wherein the thickness of said first ground plane isless than or equal to 5 μm.
 5. The chip mounting system of claim 1,wherein said conductive plane comprises a power supply distributionplane.
 6. The chip mounting system of claim 1, wherein said conductiveplane comprises a copper plane.
 7. The chip mounting system of claim 1,wherein said conductive plane comprises an aluminum plane.
 8. The chipmounting system of claim 1, wherein said multi-layer structure furthercomprises a first insulating layer provided on the side said multi-layerstructure directly adjacent to said substrate.
 9. The chip mountingsystem of claim 8, wherein said first insulating layer comprises asilicon dioxide layer.
 10. The chip mounting system of claim 9, whereinthe thickness of said silicon dioxide layer is 0.1 to 0.5 μm.
 11. Thechip mounting system of claim 8, wherein said conductive plane isdeposited over said first insulating layer.
 12. The chip mounting systemof claim 1, wherein said insulating layer comprises a second insulatinglayer formed over said conductive plane.
 13. The chip mounting system ofclaim 1, wherein said multi-layer structure further comprises a thirdinsulating layer formed over said signal wiring layer.
 14. The chipmounting system of claim 13, wherein said multi-layer structure furthercomprises a second conductive plane formed over said third insulatinglayer.
 15. The chip mounting system of claim 12, wherein said secondinsulating layer comprises silicon dioxide.
 16. The chip mounting systemof claim 12, where the thickness of said second insulating is 0.5 to 4.0μm.
 17. The chip mounting system of claim 1, wherein said signal wiringlayer comprises at least one signal line.
 18. The chip mounting systemof claim 17, wherein said at least one signal line is 6 to 10 μm wide.19. The chip mounting system of claim 13, wherein said third insulatinglayer comprises a silicon dioxide layer.
 20. The chip mounting system ofclaim 14, wherein the thickness of said second conductive plane is 3 μmto 5 μm.
 21. The chip mounting system of claim 17, wherein said at leastone signal line is terminated at a bond pad.
 22. The chip mountingsystem of claim 12, wherein said second insulating layer comprises apolyimide layer.
 23. The chip mounting system of claim 13, wherein saidthird insulating layer comprises a silicon dioxide layer.
 24. The chipmounting system of claim 13, wherein said third insulating layercomprises a polyimide layer.
 25. The chip mounting system of claim 14,wherein said second conductive plane comprises a ground plane.
 26. Thechip mounting system of claim 14, wherein said second conductive planecomprises a power supply distribution plane.
 27. The chip mountingsystem of claim 14, wherein said multi-layer structure further comprisesa fourth insulating layer formed over said second conductive plane. 28.A chip mounting system comprising: a substrate for mounting at least onechip, said substrate having at least one through-hole; a multi-layerstructure covering both sides of said substrate and passing through saidthrough-hole, said multi-layer structure comprising a conductive planeand a signal wiring layer having traces terminating in bond pads, saidconductive plane and said signal wiring layer having an insulating layerinterposed between them; and said at least one chip mounted onto saidbond pads.
 29. The chip mounting system of claim 28, wherein saidthrough-hole is rectangular in shape.
 30. The chip mounting system ofclaim 28, wherein said through-hole is circular in shape.
 31. The chipmounting system of claim 28 further comprising interconnect wiring tocarry a signal between said bond pads and respective traces of saidsignal wiring layer.
 32. The chip mounting system of claim 28 furthercomprising interconnect wiring to carry a signal between respectivetraces of said signal wiring layer and active and/or passive componentson the surface of said substrate.
 33. The chip mounting system of claim28, wherein said conductive plane comprises a first ground plane. 34.The chip mounting system of claim 34, wherein said first ground plane isat least 3 μm thick.
 35. The chip mounting system of claim 34, whereinthe thickness of said first ground plane is less than or equal to 5 μm.36. The chip mounting system of claim 28, wherein said conductive planecomprises a power supply distribution plane.
 37. The chip mountingsystem of claim 28, wherein said conductive plane comprises a copperplane.
 38. The chip mounting system of claim 28, wherein said conductiveplane comprises an aluminum plane.
 39. The chip mounting system of claim28, wherein said multi-layer structure further comprises a firstinsulating layer provided on the side said multi-layer structuredirectly adjacent to said substrate.
 40. The chip mounting system ofclaim 39, wherein said first insulating layer comprises a silicondioxide layer.
 41. The chip mounting system of claim 40, wherein thethickness of said silicon dioxide layer is 0.1 to 0.5 μm.
 42. The chipmounting system of claim 39, wherein said conductive plane is depositedover said first insulating layer.
 43. The chip mounting system of claim28, wherein said insulating layer comprises a second insulating layerformed over said conductive plane.
 44. The chip mounting system of claim28, wherein said multi-layer structure further comprises a thirdinsulating layer formed over said signal wiring layer.
 45. The chipmounting system of claim 44, wherein said multi-layer structure furthercomprises a second conductive plane formed over said third insulatinglayer.
 46. The chip mounting system of claim 43, wherein said secondinsulating layer comprises silicon dioxide.
 47. The chip mounting systemof claim 43, where the thickness of said second insulating is 0.5 to 4.0μm.
 48. The chip mounting system of claim 28, wherein said signal wiringlayer comprises at least one signal line.
 49. The chip mounting systemof claim 48, wherein said at least one signal line is 6 to 10 μm wide.50. The chip mounting system of claim 44, wherein said third insulatinglayer comprises a silicon dioxide layer.
 51. The chip mounting system ofclaim 45, wherein the thickness of said second conductive plane is 3 μmto 5 μm.
 52. The chip mounting system of claim 48, wherein said at leastone signal line is terminated at a bond pad.
 53. The chip mountingsystem of claim 43, wherein said second insulating layer comprises apolyimide layer.
 54. The chip mounting system of claim 44, wherein saidthird insulating layer comprises a silicon dioxide layer.
 55. The chipmounting system of claim 44, wherein said third insulating layercomprises a polyimide layer.
 56. The chip mounting system of claim 45,wherein said second conductive plane comprises a ground plane.
 57. Thechip mounting system of claim 45, wherein said second conductive lanecomprises a power supply distribution plane.
 58. The chip mountingsystem of claim 45, wherein said multi-layer structure further comprisesa fourth insulating layer formed over said second conductive plane. 59.A processor system comprising: a processor; and memory device coupled tosaid processor, said processor and memory device residing on a commonsubstrate, said substrate having a through-hole, said substrate furthercomprising a top side and a bottom side with multi-layer structureinterposed on both sides of said substrate and passing through saidthrough-hole, said multi-layer structure comprising: a conductive plane;and a signal wiring layer, said conductive plane and said signal wiringlayer having an insulating layer interposed between them.
 60. Theprocessor system of claim 59, wherein said conductive plane comprises afirst ground plane.
 61. The processor system of claim 60, wherein saidfirst ground plane is at least 3 μm thick.
 62. The processor system ofclaim 60, wherein the thickness of said first ground plane is less thanor equal to 5 μm.
 63. The processor system of claim 59, wherein saidconductive plane comprises a power supply distribution plane.
 64. Theprocessor system of claim 59, wherein said conductive plane comprises acopper plane.
 65. The processor system of claim 59, wherein saidconductive plane comprises an aluminum plane.
 66. The processor systemof claim 59, wherein said multi-layer structure further comprises afirst insulating layer provided on the side said multi-layer structuredirectly adjacent to said substrate.
 67. The processor system of claim66, wherein said first insulating layer comprises a silicon dioxidelayer.
 68. The processor system of claim 67, wherein the thickness ofsaid silicon dioxide layer is 0.1 to 0.5 μm.
 69. The processor system ofclaim 66, wherein said conductive plane is deposited over said firstinsulating layer.
 70. The processor system of claim 59, wherein saidinsulating layer comprises a second insulating layer formed over saidconductive plane.
 71. The processor system of claim 59, wherein saidmulti-layer structure further comprises a third insulating layer formedover said signal wiring layer.
 72. The processor system of claim 71,wherein said multi-layer structure further comprises a second conductiveplane formed over said third insulating layer.
 73. The processor systemof claim 70, wherein said second insulating layer comprises silicondioxide.
 74. The processor system of claim 70, where the thickness ofsaid second insulating is 0.5 to 4.0 μm.
 75. The processor system ofclaim 59, wherein said signal wiring layer comprises at least one signalline.
 76. The processor system of claim 75, wherein said at least onesignal line is 6 to 10 μm wide.
 77. The processor system of claim 71,wherein said third insulating layer comprises a silicon dioxide layer.78. The processor system of claim 72, wherein the thickness of saidsecond conductive plane is 3 μm to 5 μm.
 79. The processor system ofclaim 75, wherein said at least one signal line is terminated at a bondpad.
 80. The processor system of claim 70, wherein said secondinsulating layer comprises a polyimide layer.
 81. The processor systemof claim 71, wherein said third insulating layer comprises a silicondioxide layer.
 82. The processor system of claim 71, wherein said thirdinsulating layer comprises a polyimide layer.
 83. The processor systemof claim 72, wherein said second conductive plane comprises a groundplane.
 84. The processor system of claim 72, wherein said secondconductive plane comprises a power supply distribution plane.
 85. Theprocessor system of claim 72, wherein said multi-layer structure furthercomprises a fourth insulating layer formed over said second conductiveplane.
 86. A integrated circuit package comprising: a substrate formounting at least one chip, said substrate having at least onethrough-hole; a multi-layer structure covering both sides of saidsubstrate and passing through said through-hole, said multi-layerstructure comprising a conductive plane and a signal wiring layer, saidconductive plane and said signal wiring layer having an insulating layerinterposed between them; and a integrated circuit package to encase saidsubstrate, said multi-layer structure and at least one circuit chip. 87.The integrated circuit package of claim 86, wherein said conductiveplane comprises a first ground plane.
 88. The integrated circuit packageof claim 87, wherein said first ground plane is at least 3 μm thick. 89.The integrated circuit package of claim 87, wherein the thickness ofsaid first ground plane is less than or equal to 5 μm.
 90. Theintegrated circuit package of claim 86, wherein said conductive planecomprises a power supply distribution plane.
 91. The integrated circuitpackage of claim 86, wherein said conductive plane comprises a copperplane.
 92. The integrated circuit package of claim 86, wherein saidconductive plane comprises an aluminum plane.
 93. The integrated circuitpackage of claim 86, wherein said multi-layer structure furthercomprises a first insulating layer provided on the side said multi-layerstructure directly adjacent to said substrate.
 94. The integratedcircuit package of claim 93, wherein said first insulating layercomprises a silicon dioxide layer.
 95. The integrated circuit package ofclaim 94, wherein the thickness of said silicon dioxide layer is 0.1 to0.5 μm.
 96. The integrated circuit package of claim 93, wherein saidconductive plane is deposited over said first insulating layer.
 97. Theintegrated circuit package of claim 86, wherein said insulating layercomprises a second insulating layer formed over said conductive plane.98. The integrated circuit package of claim 86, wherein said multi-layerstructure further comprises a third insulating layer formed over saidsignal wiring layer.
 99. The integrated circuit package of claim 98,wherein said multi-layer structure further comprises a second conductiveplane formed over said third insulating layer.
 100. The integratedcircuit package of claim 97, wherein said second insulating layercomprises silicon dioxide.
 101. The integrated circuit package of claim97, where the thickness of said second insulating is 0.5 to 4.0 μm. 102.The integrated circuit package of claim 86, wherein said signal wiringlayer comprises at least one signal line.
 103. The integrated circuitpackage of claim 102, wherein said at least one signal line is 6 to 10μm wide.
 104. The integrated circuit package of claim 98, wherein saidthird insulating layer comprises a silicon dioxide layer.
 105. Theintegrated circuit package of claim 99, wherein the thickness of saidsecond conductive plane is 3 μm to 5 μm.
 106. The integrated circuitpackage of claim 102, wherein said at least one signal line isterminated at a bond pad.
 107. The integrated circuit package of claim97, wherein said second insulating layer comprises a polyimide layer.108. The integrated circuit package of claim 98, wherein said thirdinsulating layer comprises a silicon dioxide layer.
 109. The integratedcircuit package of claim 98, wherein said third insulating layercomprises a polyimide layer.
 110. The integrated circuit package ofclaim 99, wherein said second conductive plane comprises a ground plane.111. The integrated circuit package of claim 99, wherein said secondconductive plane comprises a power supply distribution plane.
 112. Theintegrated circuit package of claim 99, wherein said multi-layerstructure further comprises a fourth insulating layer formed over saidsecond conductive plane.
 113. A method of forming a chip carrier, saidmethod comprising: forming a conductive plane on both sides of asubstrate and in at least one through-hole of said substrate; forming atleast one insulating layer over said conductive plane and in at leastone through-hole of said substrate; and forming a signal wiring layerover said at least one insulating layer and in at least one through-holeof said substrate.
 114. The method of claim 113, wherein said forming ofsaid at least one insulating layer comprises forming a silicon dioxidelayer.
 115. The method of claim 113, wherein said forming of saidconductive plane is by simple evaporation.
 116. The method of claim 113,wherein said forming of said conductive plane is by sputtering.
 117. Themethod of claim 113, wherein said forming of said conductive plane is byelectroplating.
 118. The method of claim 113, wherein said forming ofsaid at least one insulating layer is by chemical vapor deposition. 119.The method of claim 113, wherein said forming of said at least oneinsulating layer is by spin coating.
 120. The method of claim 113,wherein said forming of said signal wiring layer comprises forming atleast one signal line.
 121. The method of claim 120, wherein saidforming of said at least one signal line is by optical lithography. 122.The method of claim 120, wherein said forming of said at least onesignal line is by optical lithography followed by additivemetallization.
 123. The method of claim 122, wherein said additivemetallization is performed by liftoff by evaporation.
 124. The method ofclaim 123, wherein said additive metallization is performed byelectroplating.
 125. The method of claim 113 further comprisingfabricating interconnect wiring between said substrate and said signalwiring layer.
 126. The method of claim 113 further comprisingfabricating interconnect wiring between said signal wiring layer andchips mounted on said substrate.
 127. A method of forming a chipcarrier, said method comprising: forming a first insulating layer onboth sides of a substrate and in at least one through-hole of saidsubstrate; forming a conductive plane over said first insulating layerand in at least one through-hole of said substrate; forming a secondinsulating layer over said conductive plane and in at least onethrough-hole of said substrate; and forming a signal wiring layer oversaid second insulating layer and in at least one through-hole of saidsubstrate.
 128. The method of claim 127 further comprising forming athird insulating layer over said signal wiring layer and in at least onethrough-hole of said substrate.
 129. A method of forming a chip carrier,said method comprising: forming a first insulating layer on both sidesof a substrate and in at least one through-hole of said substrate;forming a first conductive plane over said first insulating layer and inat least one through-hole of said substrate; forming a second insulatinglayer over said first conductive plane and in at least one through-holeof said substrate; fabricating signal lines over said second insulatinglayer and in at least one through-hole of said substrate; forming athird insulating layer over said signal lines and in at least onethrough-hole of said substrate; forming a second conductive plane oversaid third insulating layer and in at least one through-hole of saidsubstrate; forming a fourth insulating layer over said second conductiveplane and in at least one through-hole of said substrate; and mounting aplurality of integrated circuit chips over said fourth insulating layer.130. The method of claim 129 further comprising fabricating interconnectwiring between said signal lines and said integrated circuit chips. 131.The method of claim 129 further comprising fabricating interconnectwiring between said signal lines and active and/or passive components onsaid substrate.